1. Field of the Invention
This invention relates to a circuit for impedance matching for testing devices for low output impedance devices, particularly CMOS devices.
2. Brief Description of the Prior Art
Integrated circuit devices which have a lower output impedance than the transmission line (e.g., stripline, microstrip, coaxial line, etc.) which the integrated circuit device is driving will cause the output waveform to oscillate due to reflections of the incident waveform. The time required for this oscillation to dampen is dependent upon the electrical length of the transmission line.
Terminating the transmission line at the end of the line with an equivalent matching resistor is not an optimum solution. CMOS integrated circuits typically have substantially less than 50 ohms output impedance. The typical transmission line is 50 to 100 ohms. CMOS devices have evolved into low power high speed logic devices. Therefore, the addition of a 50 ohm to 100 ohm termination resistor at the end of the transmission line on all outputs would significantly increase the power dissipation, thereby defeating a key advantage for using CMOS (low power consumption).
By adding a resistor in series with the device output (between the device and the transmission line) to match the transmission line impedance, the reflections that cause the oscillation will be eliminated. However, this series termination of the outputs of CMOS devices reduces the high logic level output current (IOH) and low logic level output current (IOL) which the CMOS device can drive. The output impedances of these CMOS logic devices are deliberately low in order to drive high IOH and IOL currents.
Known prior art CMOS testing devices include the Teradyne J971 which has diodes and programmable voltages to clamp the reflections at the nominal output voltage levels. There are several problems associated with this method. One problem is that, in order to clamp the voltage at the nominal levels, the diode must have a significant idle current supplied by the device under test (DUT) output in the static state. Further, though the voltage levels are clamped at the nominal output voltages, there is still significant stray transient current (about 40 ma) while the DUT is switching to the next state. This stray transient current can cause timing skews and affect the output waveform edges at the end of the transmission line.
The Trillium Tester switches a 50 ohm termination resistor dynamically to terminate the 50 ohm transmission line. This 50 ohm termination attenuates the DUT output. Then the comparator levels must be adjusted based upon the attenuation ratio. Also, the switching spikes caused by dynamically switching the termination resistors is not desirable.
None of the above described test methods recreate the way the CMOS device is used in the final application.
It is common practice to place a 50 ohm ohm termination resistor in series with a large capacitor at the end of the transmission line. This method attenuates the DUT output based upon the ratio of the output resistance of the DUT and the 50 ohm termination. Then there is a large RC time constant required for the DUT output to reach the nominal voltage level between states. The method causes timing skews and affects the output waveform edges at the end of the transmission line based upon the large RC time constant.